1. Field of the Invention
The present invention relates to a data processing system having multiple data cache devices which monitor a system bus to maintain cache coherency. More particularly, the invention is a method of controlling a data transfer operation such that the need to reorder bus transactions in response to a request for data by another device monitoring the bus is eliminated.
2. Background of the Invention
Conventional systems are known which implement what is commonly referred to as "snooping" in order to monitor a system bus for the memory address of the data that the device is modifying. Generally, when more than one device, which includes a cache, is capable of modifying data stored at a particular memory address the devices perform bus snooping to determine whether another device has requested the same data which is owned (the device has been granted access to the data) by the device doing the modifying. The requesting device places the memory address for the desired data on the system bus and the device which owns the data monitors the bus for this address. The device owning the data compares the memory address on the bus with the memory address of the data being modified, and if the addresses are the same a "snoop hit" is said to have occurred. The conventional response to a snoop hit is to perform a "snoop push" operation which causes the modifying device to immediately push, or transfer, the data back to memory. This snoop push requires all pending bus transaction operations to be reordered such that the transactions that implement the snoop push are executed first. A great deal of complex logic is required to perform this reordering of bus transactions.
For example, a modifying device (such as a central processing unit), or the like performs a read with intent to modify operation which reads the data from the system memory and stores a copy of the data in its cache. Next, the modifying device begins snooping the bus and also begins modifying the data. If the device sees the memory address of the data that it currently owns then a snoop hit occurs. Snoop hits are normally caused by another device requesting the data from memory by placing the memory address of the requested data on the system bus.
Generally, when a snoop hit occurs the device which has modified the data must reorder its bus transaction queue and transfer the modified data back to system memory in order for the requesting device to have the most up to date copy of the data, this is accomplished using a snoop push. Additionally, the requesting device must be prevented from reading the existing, or unmodified, copy of the data currently stored in memory. Often, the CPU, or other device that has modified the data is performing other operations as well. In order to perform these operations, the processor will have a sequence of bus transactions to be executed queued up. When a snoop hit occurs, these conventional processing systems must make transferring the modified data in its cache to the system memory (the snoop push) the number one priority. This forces the processor to have a mechanism that will reorder all of the bus transactions which are already in its queue such that those transactions required to implement the snoop push are executed first. A great deal of complex logic is needed in order to implement a snoop push operation.
Therefore, it can be readily understood how a system which utilizes specific control signals to avoid the necessity of ever performing a snoop push operation would be advantageous since the result would be a system having greatly reduced complexity and, therefore, less physical hardware components, less hardware development time and cost.
U.S. Pat. No. 5,025,365 describes a cache coherency protocol wherein a "Purge Command" is used to cause the data to be returned to memory and the device modifying the data to mark its copy as invalid. U.S. Pat. No. 5,072,369 is an interface for providing cache coherency between buses. A bus interface circuit places a signal on one of the buses telling the bus master to copy data from the cache into main memory before the interface circuit performs a main memory access. European patent application 0 309 994 describes a computer having a specific function which clears, or flushes, the contents of a cache, based on the state of a specific control signal, in order to maintain cache coherency. U.S. Pat. No. 5,097,532 also uses a flush signal to enable and disable a cache by clearing all the valid bits to insure coherency.
Additionally, the PowerPC 601 Reduced Instruction Set Computing (RISC) microprocessor (POWERPC is a trademark of IBM Corp.) uses a snoop push operation which copies back modified sectors of a cache which are hit by snooping operations. When a snoop hit occurs, this processor issues a signal which causes the system to reorder its data bus operations to push the data from its cache into system memory. For additional information regarding the POWERPC 601 microprocessor see the POWERPC 601 Microprocessor User's Guide, published by Motorola Corporation.
It can be seen that none of the conventional systems provide a protocol that will allow a processing system to avoid implementing a snoop push in response to a snoop hit.